# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=haswell -iterations=1500 -micro-op-queue-size=1 -all-views=false -summary-view < %s | FileCheck %s -check-prefix=HASWELL-UOPQ-1
# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=haswell -iterations=1500 -micro-op-queue-size=2 -all-views=false -summary-view < %s | FileCheck %s -check-prefix=HASWELL-UOPQ-2
# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=haswell -iterations=1500 -micro-op-queue-size=3 -all-views=false -summary-view < %s | FileCheck %s -check-prefix=HASWELL-UOPQ-3
# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=haswell -iterations=1500 -micro-op-queue-size=4 -all-views=false -summary-view < %s | FileCheck %s -check-prefix=HASWELL-UOPQ-4
# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=haswell -iterations=1500 -micro-op-queue-size=4 -decoder-throughput=2 -all-views=false -summary-view < %s | FileCheck %s -check-prefix=HASWELL-DEC-2

# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -iterations=1500 -micro-op-queue-size=1 -all-views=false -summary-view < %s | FileCheck %s -check-prefix=BTVER2-UOPQ-1
# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -iterations=1500 -micro-op-queue-size=2 -all-views=false -summary-view < %s | FileCheck %s -check-prefix=BTVER2-UOPQ-2
# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -iterations=1500 -micro-op-queue-size=4 -decoder-throughput=1 -all-views=false -summary-view < %s | FileCheck %s -check-prefix=BTVER2-DEC-1

add %eax, %eax
add %ebx, %ebx
add %ecx, %ecx
add %edx, %edx

# BTVER2-DEC-2:        Iterations:        1500
# BTVER2-DEC-2-NEXT:   Instructions:      6000
# BTVER2-DEC-2-NEXT:   Total Cycles:      3003
# BTVER2-DEC-2-NEXT:   Total uOps:        6000

# BTVER2-DEC-2:        Dispatch Width:    2
# BTVER2-DEC-2-NEXT:   uOps Per Cycle:    2.00
# BTVER2-DEC-2-NEXT:   IPC:               2.00
# BTVER2-DEC-2-NEXT:   Block RThroughput: 2.0

# BTVER2-DEC-1:        Iterations:        1500
# BTVER2-DEC-1-NEXT:   Instructions:      6000
# BTVER2-DEC-1-NEXT:   Total Cycles:      6003
# BTVER2-DEC-1-NEXT:   Total uOps:        6000

# BTVER2-UOPQ-1:       Iterations:        1500
# BTVER2-UOPQ-1-NEXT:  Instructions:      6000
# BTVER2-UOPQ-1-NEXT:  Total Cycles:      6003
# BTVER2-UOPQ-1-NEXT:  Total uOps:        6000

# BTVER2-UOPQ-2:       Iterations:        1500
# BTVER2-UOPQ-2-NEXT:  Instructions:      6000
# BTVER2-UOPQ-2-NEXT:  Total Cycles:      3003
# BTVER2-UOPQ-2-NEXT:  Total uOps:        6000

# HASWELL-DEC-2:       Iterations:        1500
# HASWELL-DEC-2-NEXT:  Instructions:      6000
# HASWELL-DEC-2-NEXT:  Total Cycles:      3003
# HASWELL-DEC-2-NEXT:  Total uOps:        6000

# HASWELL-UOPQ-1:      Iterations:        1500
# HASWELL-UOPQ-1-NEXT: Instructions:      6000
# HASWELL-UOPQ-1-NEXT: Total Cycles:      6003
# HASWELL-UOPQ-1-NEXT: Total uOps:        6000

# HASWELL-UOPQ-2:      Iterations:        1500
# HASWELL-UOPQ-2-NEXT: Instructions:      6000
# HASWELL-UOPQ-2-NEXT: Total Cycles:      3003
# HASWELL-UOPQ-2-NEXT: Total uOps:        6000

# HASWELL-UOPQ-3:      Iterations:        1500
# HASWELL-UOPQ-3-NEXT: Instructions:      6000
# HASWELL-UOPQ-3-NEXT: Total Cycles:      2003
# HASWELL-UOPQ-3-NEXT: Total uOps:        6000

# HASWELL-UOPQ-4:      Iterations:        1500
# HASWELL-UOPQ-4-NEXT: Instructions:      6000
# HASWELL-UOPQ-4-NEXT: Total Cycles:      1503
# HASWELL-UOPQ-4-NEXT: Total uOps:        6000

# BTVER2-DEC-1:        Dispatch Width:    2
# BTVER2-DEC-1-NEXT:   uOps Per Cycle:    1.00
# BTVER2-DEC-1-NEXT:   IPC:               1.00
# BTVER2-DEC-1-NEXT:   Block RThroughput: 2.0

# BTVER2-UOPQ-1:       Dispatch Width:    2
# BTVER2-UOPQ-1-NEXT:  uOps Per Cycle:    1.00
# BTVER2-UOPQ-1-NEXT:  IPC:               1.00
# BTVER2-UOPQ-1-NEXT:  Block RThroughput: 2.0

# BTVER2-UOPQ-2:       Dispatch Width:    2
# BTVER2-UOPQ-2-NEXT:  uOps Per Cycle:    2.00
# BTVER2-UOPQ-2-NEXT:  IPC:               2.00
# BTVER2-UOPQ-2-NEXT:  Block RThroughput: 2.0

# HASWELL-DEC-2:       Dispatch Width:    4
# HASWELL-DEC-2-NEXT:  uOps Per Cycle:    2.00
# HASWELL-DEC-2-NEXT:  IPC:               2.00
# HASWELL-DEC-2-NEXT:  Block RThroughput: 1.0

# HASWELL-UOPQ-1:      Dispatch Width:    4
# HASWELL-UOPQ-1-NEXT: uOps Per Cycle:    1.00
# HASWELL-UOPQ-1-NEXT: IPC:               1.00
# HASWELL-UOPQ-1-NEXT: Block RThroughput: 1.0

# HASWELL-UOPQ-2:      Dispatch Width:    4
# HASWELL-UOPQ-2-NEXT: uOps Per Cycle:    2.00
# HASWELL-UOPQ-2-NEXT: IPC:               2.00
# HASWELL-UOPQ-2-NEXT: Block RThroughput: 1.0

# HASWELL-UOPQ-3:      Dispatch Width:    4
# HASWELL-UOPQ-3-NEXT: uOps Per Cycle:    3.00
# HASWELL-UOPQ-3-NEXT: IPC:               3.00
# HASWELL-UOPQ-3-NEXT: Block RThroughput: 1.0

# HASWELL-UOPQ-4:      Dispatch Width:    4
# HASWELL-UOPQ-4-NEXT: uOps Per Cycle:    3.99
# HASWELL-UOPQ-4-NEXT: IPC:               3.99
# HASWELL-UOPQ-4-NEXT: Block RThroughput: 1.0
